1. Field of the Invention
The present invention relates to a semiconductor memory device that stores data dynamically. More particularly, it relates to a semiconductor device, which includes a floating semiconductor layer (body region) in each memory cell electrically separated from other memory cells to store data depending on if the body region holds the majority carrier excessively therein.
2. Description of the Related Art
A DRAM is generally employed as a semiconductor memory device having a large storage capacity and tends to have an increasingly complicated structure because of progresses in fine pattering technologies. A new DRAM is proposed to achieve a relatively simpler structure but has a difficulty in its controllability. In either case, it is very hard to achieve high integration and high performance.
JP-A 2003-68877 proposes a semiconductor memory device capable of achieving high integration and high performance because of a simple structure. This semiconductor memory device comprises body regions formed on an SOI substrate, each electrically isolated from others. A threshold voltage is altered to store data depending on if the majority carrier is held excessively in the body region.
FIG. 16 shows a sectional structure of a unit memory cell in a DRAM, which is the semiconductor memory device disclosed in JP-A 2003-68877. FIG. 17 shows an equivalent circuit diagram thereof. The memory cell MC comprises an SOI-structured N-channel MOS transistor. Namely, it employs an SOI substrate, which includes a silicon substrate 10, a silicon oxide film 11 formed thereon as an insulator film, and a P-type silicon layer formed on the silicon oxide film 11. Ions of a P-type impurity are implanted into a region of the P-type silicon layer for memory cell formation to form a body region 12. A gate electrode 13 is then formed on a gate insulator 16 above the body region 12. N-type source/drain diffusion regions 14 and 15 are formed as self-aligned with the gate electrode 13. The source/drain diffusion regions 14 and 15 have an LDD structure that includes a low resistance layer 15A formed to a depth reaching the silicon oxide film 11 on the bottom and a high resistance layer 15B extending from the low resistance layer toward the gate electrode 13.
With respect to the body region 12 beneath the gate electrode 13, the oxide film may be employed for separation in the direction of the channel width (the direction perpendicular to the page of FIG. 16). In this case, the bottom and the sides in the direction of the channel width are isolated from others, and those in the direction of the channel length are separated at PN junctions. Thus, the body region 12 is kept in the floating state. Such memory cells MC are arrayed in matrix. In this case, the gate electrode 13 is connected to a word line WL, the source diffusion region 15 to a fixed potential line (ground potential line), and the drain diffusion region to a bit line BL.
FIG. 18 shows a layout of a memory cell array. FIGS. 19 and 20 show A-A′ and B-B′ sections of FIG. 18, respectively. The body regions 12 are device-isolated and patterned in grid by a buried silicon oxide film 21 (FIG. 20). The gate electrode 13 is formed continuously in one direction to provide the word line WL. The source diffusion region 15 is formed continuously along the word line WL to provide a fixed potential line (common source line). An interlayer insulator 23 covers the transistors and the bit line BL is formed on the insulator. The bit line BL is in contact with the drain diffusion region 14 shared by two transistors (memory cells), and is located as intersecting the word line WL.
This memory cell stores data through the use of storage of holes or the majority carrier in the body region 12. When the MOS transistor contained in the memory cell operates in the pentode region, a large current flows from the drain diffusion region 14 to cause impact ionization in the vicinity of the drain diffusion region 14. The impact ionization generates electron-hole pairs. The generated holes or majority carriers are held in the body region 12. This hole storage state (a higher potential state above a state of thermal equilibrium) may be defined as data “1”, for example. A PN junction between the drain diffusion region 14 and the body region 12 is forward biased to release holes from inside the body region 12 to the drain diffusion region 14. This state is defined as data “0”.
Data “1” and “0” have a difference in potential on the body region 12 and are stored as a difference in threshold voltage of the MOS transistor. A threshold voltage Vth1 in the state of data “1” with an elevated potential on the body region 12 due to the storage of holes is lower than a threshold voltage Vth0 in the state of data “0”. It is required to apply a negative bias voltage to the word line to retain the state of data “1” with the majority carrier or holes stored in the body region 12. This data retaining state can not be changed on reading until writing (erasing) of opposite data is executed. Different from a 1-transistor/1-capacitor DRAM that employs storage of charge in a capacitor, non-destructive reading can be performed.
Such the DRAM has a problem because holes stored in the body region in one memory cell may flow into the body region in an adjacent memory cell through a parasitic bipolar transistor to vary or destroy data in the adjacent memory cell possibly (disturbance by the parasitic bipolar transistor). This problem is described specifically. For example, as shown in FIG. 21, in a memory cell MCL data “1” is stored because holes are held excessively in the body region 12. In contrast, in a memory cell MCR adjoining to and sharing the bit line BL with the memory cell MCL, data “0” is stored because holes are not held in the body region 12.
When the memory cell MCL is rewritten from “1” to “0” in this state, the voltage on the bit line BL shared by the memory cells MCR and MCL is changed from “H” to “L”. As a result, holes in the body region 12 (p-type) of the memory cell MCL are injected therefrom into the drain diffusion region 14 (n-type) connected to the bit line BL. The injected holes disappear when they recombine with electrons or the majority carrier in the n-type drain diffusion region 14. In this case, because of a long diffusion length of the hole, part of the holes may possibly flow into the body region 12 (p-type) in the adjacent memory cell MCR and destroy “0” data in the memory cell MCR. This phenomenon can not be ignored because the drain diffusion region 14 tends to have a shortened length as fine patterning of the device proceeds.